This is an algorithm IP that verifies the operation of IC Memory functions.
It applies a pattern to measurement target and compares the output signal and the expected value and judge Pass/Fail. This IP is aimed at confirming logic operation of IC Memory.
Actual use case is shown below.
- Confirm logical operation.
- Grade screening Test.
- Operating margine Test.
- Evaluation and analysis of the defective cells.
Revision contents on Rev 1.07.04
Condition Table Memory_TypeF License(PCXA01-3004)
When VIH/VIL is outside the range of the voltage generation or the voltage generation amplitude in [Condition Table], the specification has been changed to generate an error.
Timing Search for Memory_TypeF Lisence (PCXA01-M3007)
Fixed an issue where all timing edges of pins (or pin groups) specified in the [High Resolution Timing] tab were searched with high resolution.
Timing edges that are not specified in the [High Resolution Timing] tab are searched with normal resolution.
- Various input waveforms is available.
- Can specify The input voltage of each pin individually.
- Can specify pattern program (combination of input value and expected value) to the measurement target.
- Can specify the current load and termination for each pin.
- Can specify the power-on/off sequence for power supply and input/output pin.
- Supports the following licenses.